Integrity 3D-IC Platform

The Cadence Integrity 3D-IC Platform is a comprehensive design and analysis solution tailored for multi-chiplet systems. It leverages the Innovus Implementation System infrastructure to facilitate the planning, implementation, and analysis of stacked die systems across various packaging styles, including 2.5D and 3D configurations.

This platform stands out as the industry's first integrated solution that supports both system-level and SoC-level analysis, enabling seamless co-design with Cadence's Virtuoso and Allegro environments. It offers a unified environment where engineers can simultaneously plan and construct multiple chiplets using a multi-technology database.

Key Benefits

• Productivity: Engineers can efficiently plan and build chiplets in a unified environment.
• Design Robustness: Integrated electrothermal and physical checks ensure reliability.
• System-Driven PPA: Early system-level analysis feedback enhances chip-level power, performance, and area.
• Ease of Use: A single planning cockpit and hierarchical database streamline flow management and results analysis.

The platform supports advanced packaging configurations such as fan-out wafer-level packaging (FOWLP), silicon interposer (2.5D), and full 3D stacking. It incorporates a complete 3D-IC stack planning system, allowing for efficient management and implementation of 3D designs.

Seamless integration with the Innovus Implementation System provides ease-of-use through script-based integration for high-capacity digital designs, including 3D die partitioning, optimization, and timing flows. The platform's integrated system-level analysis capabilities enable robust 3D-IC design through early electrothermal and cross-die static timing analysis, offering early feedback for system-driven PPA.

With a common cockpit and database, SoC and package design teams can co-optimize the entire system concurrently, incorporating system-level feedback efficiently. The native 3D capabilities allow users to partition a 2D design into a 3D multi-tier design using 3D mixed placer technology. Co-design with analog and packaging platforms is facilitated, enabling faster design closure and improved productivity.

The user-friendly interface includes a powerful cockpit for interactive results analytics and run management, providing valuable insights into design metrics.